Exp From 7.0 Yrs To 11.0 Yrs        India - Bangalore

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Job Description

Job ID - 0660990004

Job Details - The successful candidate will be involved in hands-on implementation of complex networking ASIC and will be responsible for IP/sub-system level micro-architecture development and RTL coding.  The candidate will work on every aspect of ASIC design: processing and collaborating closely with the SW, FW, and verification teams.  The candidate must have a good understanding of digital design fundamentals and a strong background of ASIC design and verification. Must have experience in any of the industry standards tools.  Should be familiar with synthesis and timing closure flows and concepts. 

  1. Must have exposure to networking in education or experience
  2. Must have developed a hardware module that is more than 2000 lines of code
  3. Must have background in RTL design using Verilog
  4. Must have experience with Scatter Gather DMA
  5. Desire to create & patent new ideas
  6. Knowledge of  scripting languages such as perl, python, etc.
  7. Preferred background in architecture definition.
  8. Self-driven/motivated – “How can I make an impact or difference” attitude
  9. Desire to work in team environment
  10. Desire to be exposed to all aspects of business model
  11. DMA Experience

Industry: IT-Software/Software Services
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Contact Person: Ashwini
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